View RAA230215GSB_8380078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r18ds0013ej0102 rev.1.01 page 1 of 34 jul 23, 2014 datasheet raa23021x 5.5v input, 3a, step-down dc/dc converter + ldo description the raa23021x is a high efficiency monolithic step-down dc/dc synchronous converter plus a ldo (low dropout) regulator which has an ultra-low power mode. features ? dc/dc converter (ch1) ? synchronous rectification type step-down circuit ? integrated power mosfets ? preset output voltage (there are also products that have adjustable output voltage using external resistors.) ? internal phase compensator ? switching frequency: 1 mhz (fixed) ? internal timer-latch-type short-circ uit protector (fixed delay time) ? 100% duty cycle operation ? ldo (ch2) ? 500ma ? internal over current protector (foldback-current limiting) ? ultra low-power save mode (25ua typical) ? common features ? internal rise up sequencer ? internal digital soft-start functi on (2 ms fixed soft-start time) ? internal discharge circuit ? power good function ? internal timer-latch-type therma l shutdown circuit (shutdown temperature: 150c or higher) ? internal recovery-type under voltage lockout circuit application ? communication ? industrial ? building ? smart meter and, usable around mcu, asic, fpga, etc. ordering information ordering part no. package tape and reel raa230214gsb#ha0 RAA230215GSB#ha0 20-pin htssop embossed taping. 2,500pcs/reel note: a quality grade of these ics is ?standard ?. recommended applications are indicated below. computers, office equipment, co mmunications equipment, test and measurement equipment, audio and visual equipment, home electronic ap pliances, machine tools, personal electronic equipment, and industrial robots, etc. r18ds0013ej0102 rev.1.02 jul 23, 2014
raa23021x r18ds0013ej0102 rev.1.02 page 2 of 34 jul 23. 2014 part no summary part no. output input voltage output voltage maximum output current switching frequency package ch1 ch2 raa230214gsb ch1:dc/dc (step-down, current mode) ch2:ldo 3.0 v to 5.5 v 3.3 3.3 ch1:3 a ch2:0.5 a 1 mhz (fixed) 20-pin htssop RAA230215GSB 0.9 v to vin 0.8 (adjustable each output individually by external resistor) circuit example (RAA230215GSB)
raa23021x r18ds0013ej0102 rev.1.02 page 3 of 34 jul 23. 2014 block diagram ch1/ch2: preset output voltage by internal resistor. sequence pattern 1 (ch1 followed by ch2) shdnb1 pg pgnd1 lout1 out2 vin ii2 dstb ch1 or ch2 micro controller ii1 ch1 out shdnb2 agnd test1 test2 test3 av dd + + ? 0.8v e/a1 vp in1 ch2 out ch1 out ldo vp in2 phase compensator oscillator osc under voltage lockout circuit uvlo control control circuit ? on/off ? soft start ? discharge test circuit short-circuit protection circuit scp thermal shutdown circuit tsd output control (current mode /current limit) discharge control discharge control reference voltage v ref internal power supply v reg v reg v reg
raa23021x r18ds0013ej0102 rev.1.02 page 4 of 34 jul 23. 2014 ch1/ch2: adjustable output voltage by external resistor. sequence pattern 2 (ch2 followed by ch1) shdnb1 pg pgnd1 lout1 out2 vin ii2 dstb ch1 or ch2 ii1 ch1 out shdnb2 agnd test1 test2 test3 av dd + + ? 0.8v e/a1 vp in1 ch2 out ch1 out ldo vp in2 micro controller phase compensator oscillator osc under voltage lockout circuit uvlo control control circuit ? on/off ? soft start ? discharge test circuit short-circuit protection circuit scp thermal shutdown circuit tsd output control (current mode /current limit) discharge control discharge control reference voltage v ref internal power supply v reg v reg v reg
raa23021x r18ds0013ej0102 rev.1.02 page 5 of 34 jul 23. 2014 pin configuration pin function pin no. symbol i/o function 1 test1 ? test pin 1 (connect to agnd) 2 ii1 input inverted input for error amplifier of ch1 3 pgnd11 ground power ground 4 pgnd12 ground power ground 5 lout11 output inductor connection 1 for ch1 6 lout12 output inductor connection 2 for ch1 7 vp in11 power supply output stage power input 1 of ch1 8 vp in12 power supply output stage power input 2 of ch1 9 vp in2 power supply output stage power input of ch2 10 out2 output output of ch2 11 ii2 input inverted input for error amplifier of ch2 12 pg output power-goo d output (open-drain) 13 av dd power supply analog block power supply 14 agnd ground analog ground 15 test2 ? test pin 2 (connect to v reg ) 16 v reg output internal power supply output (connect 1uf) 17 test3 ? test pin 3 (open) 18 dstb input light-load operation mode setting pin 19 shdnb2 input output on/off of ch2 20 shdnb1 input output on/off of ch1 (top view)
raa23021x r18ds0013ej0102 rev.1.02 page 6 of 34 jul 23. 2014 absolute maximum ratings (unless otherwise specified, t a = 25c) parameter symbol ratings unit condition analog power supply (av dd pin) av dd ?0.5 to +6.5 v av dd vp in pin applied voltage vp in ?0.5 to +6.5 v vp in11 , vp in12 , vp in2 shdnb pin applied voltage v shdnb ?0.5 to +6.5 v shdnb1, shdnb2 dstb pin applied voltage v dstb ?0.5 to +6.5 v dstb pg pin applied voltage v pg ?0.5 to +6.5 v pg ii pin applied voltage v ii ?0.5 to +6.5 v ii1, ii2 vp in11 +vp in12 pin sink current (peak) ip in1(peak)? 3500 ma vp in11 +vp in12 lout11+lout12 pin output source current (peak) i lo1(peak)+ 3500 ma lout11, lout12 vp in2 pin sink current (dc) ip in2(dc)? 500 ma vp in2 out2 pin output source current (dc) i o2(dc)+ 500 ma out2 lout11+lout12, out2 pin output source current (dc) i lo1,o2(dc)? 100 ma when discharge circuit is operation. total power dissipation p t 3400 * 1 mw t a +25c operating ambient temperature t a ?40 to +85 c junction temperature t j ?40 to +150 c storage temperature t stg ?55 to +150 c note: * 1 this is the value at t a +25c. at t a > +25c, the total power dissipation is derated by 34mw/c. board specification : 4-layers glass e poxy board, 76.2mm x 114.3mm x 1.664mm. copper coverage area: 50%, 0.070mm thickness (top and bottom layers) 95%, 0.035mm thickness ( layers 2 and 3). connecting exposed pad caution: product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditio ns that ensure t hat the absolute maximum ratings are not exceeded. recommended operating condition (unless otherwise specified, t a = 25c) parameter symbol min typ max unit condition analog power supply voltage (av dd pin) av dd 3.0 5.0 5.5 v av dd vp in pin applied voltage vp in ? av dd ? v vp in11 , vp in12 , vp in2 shdnb pin applied voltage v shdnb 0 ? av dd v shdnb1, shdnb2 dstb pin applied voltage v dstb 0 ? av dd v dstb pg pin applied voltage v pg 0 ? av dd v pg ii pin applied voltage v ii 0 ? av dd v ii1, ii2 v reg pin capacitance c reg ? 1.0 ? f v reg operating junction temperature t jo ?40 ? +125 c
raa23021x r18ds0013ej0102 rev.1.02 page 7 of 34 jul 23. 2014 electrical characteristics (unless otherwise specified, t a = 25c, av dd = vp in1 = vp in2 = 5.0 v, vout2 = 3.3 v, f osc = 1 mhz, dstb = l) parameter symbol min typ max unit condition total standby current i dd(stnby) ? 1 2 a ai dd +ip in1 +ip in2 shdnb1 = shdnb2 = agnd circuit operation current 1 i dd1 ? 1.2 2 ma ai dd , shdnb1 = shdnb2 = av dd dstb = gnd (normal mode) circuit operation current 2 i dd2 ? 25 45 a ai dd , shdnb1 = shdnb2 = av dd dstb = av dd (ultra low-power mode) internal power supply block (v reg ) internal power supply voltage v reg 2.25 2.4 2.55 v i reg = 0ma under voltage lock out circuit (uvlo) operation start voltage during rise time av dd(l-h) 2.7 2.9 3.0 v av dd pin voltage is detected operation stop voltage av dd(h-l) 2.6 2.8 3.0 v av dd pin voltage is detected short-circuit protection circuit (scp) ii1 input detection voltage (ch1) v th(ii)1 65 75 85 % ii1 pin, ratio to the output voltage or e/a1 threshold voltage delay time t (dly) ? 10 20 ms oscillation block oscillation frequency f osc ? 1000 ? khz soft start block soft start time t ss 0.9 2.0 4.0 ms ch1, ch2 pwm block maximum duty d max.(pwm) ? 100 ? % ch1 output voltage accuracy (with resistor inside) ch1 output voltage accuracy v out1 ?2.5 ? +2.5 % i o1 = 200ma, (with internal resistor) ch2 output voltage accuracy v out2 ?1 ? +1 % i o2 = 10ma, (with internal resistor) e/a block (with resistor outside) e/a 1 input threshold voltage v ith1 0.780 0.800 0.820 v including input offset, (with external resistor) e/a 2 input threshold voltage v ith2 0.792 0.800 0.808 v including input offset, (with external resistor) output block p-ch on resistance r on-p1 ? 0.15 0.3 i o = 100ma n-ch on resistance r on-n1 ? 0.15 0.3 i o = ?100ma discharging circuit block ch1 on resistance r ondc1 ? 100 200 ch1, i dc = 20ma ch2 on resistance r ondc2 ? 200 400 ch2, i dc = 20ma series regulator block (ch2, dstb = agnd: normal mode) the voltage between the input and output v dif2 0.5 ? ? v i o2 = 20ma input regulation reg in2 ? ? 50 mv i o2 = 20ma, vp in = 3.0v to 5.5v load regulation reg l2 ? ? 50 mv i o2 = 1ma to 500ma output short-circuit current i o2short ? 100 ? ma out2=agnd peak output current i o2peak 550 ? ? ma series regulator block (ch2, dstb = av dd : ultra low-power mode) the voltage between the input and output v dif2 0.5 ? ? v i o2 = 10 a input regulation reg in2 ? ? 100 mv i o2 = 10 a, vp in = 3.0v to 5.5v load regulation reg l2 ? ? 100 mv i o2 = 10 a to 50ma
raa23021x r18ds0013ej0102 rev.1.02 page 8 of 34 jul 23. 2014 electrical characteristics (cont.) (unless otherwise specified, t a = 25c, av dd = vp in1 = vp in2 = 5.0 v, vout2 = 3.3 v, f osc = 1 mhz, dstb = l) parameter symbol min typ max unit condition power-good circuit block threshold voltage v th(pg) 86 90 94 % pg = "hiz" "l", "l" "hiz" ratio to the output voltage pg pin output voltage v pg ? ? 0.1 v i pg? = 0.1ma pg pin leakage current i leak-pg ? ? 1 a shdnb1, shdnb2 = agnd delay time t dly-pg ? ? 2 ms time from detecting of output startup until change form l to hiz on pg pin on/off controller block threshold voltage v th 0.6 ? 1.4 v shdnb1, shdnb2, dstb
raa23021x r18ds0013ej0102 rev.1.02 page 9 of 34 jul 23. 2014 typical performance characteristics (unless otherwise specified, t a = 25c, av dd = vp in1 = vp in2 = 5.0 v) efficiency vs. output current (ch1) vout=2.5v vout=3.3 v vout=1.2v vout=1.8 v
raa23021x r18ds0013ej0102 rev.1.02 page 10 of 34 jul 23. 2014 load step transient waveforms ta = 25c, vin = 5v, l1 = 2.2uh, cin1 = cin2 = 10uf, cout1 = 20uf, cout2 = 10uf ch1 vout1 200mv/div. iout1 1a/div. vout1 200mv/div. iout1 1a/div. 0.02a 3a 0.02a 3a ch2 normal operation vout2 50mv/div. iout2 0.2a/div. 0a 0.5a vout2 50mv/div. iout2 0.2a/div. 0.25a 0a vout2 20mv/div. iout2 0.05a/div. iout2 0.05a/div. vout2 20mv/div. 0a 0a 0.1a 0.1a 100us/div. 100us/div. 100us/div. 100us/div. 100us/div. 100us/div. vout1=3.3v vout1=1.2v ch1 vout2=3.3v vout2=1.2v ch2 normal operation ch2 ultra low-power mode ch2 ultra low-power mode vout2=3.3v vout2=1.2v
raa23021x r18ds0013ej0102 rev.1.02 page 11 of 34 jul 23. 2014 ch1 operation waveforms vout1 50mv/div. lout1 2v/div. il1 0.5a/div. vout1 50mv/div. lout1 2v / div. il1 0.1a / div. vout1=3.3v, iout1=1a vout1=3.3v, iout1=0.01a 0.4us/div. 0.4us/div. vout1 50mv/div. lout1 2v/div. il1 0.1a/div. vout1=3.3v, iout1=0a 4ms/div.
raa23021x r18ds0013ej0102 rev.1.02 page 12 of 34 jul 23. 2014 start-up and shutdown waveforms vout1(2.5v) 1v/div. only shdnb1 on shdnb1 5v/div. vout2(3.3v) 1v/div. shdnb2 5v/div. vout1(2.5v) 1v/div. vout2(3.3v) 1v/div. only shdnb2 on both shdnb1 and shdnb2 on at the same time vout1(2.5v) 1v/div. vout2(3.3v) 1v/div. shdnb1 shdnb2 5v/div. 2ms/div. 2ms/div. 2ms/div.
raa23021x r18ds0013ej0102 rev.1.02 page 13 of 34 jul 23. 2014 power good waveform *pg pin is connected to ch2 output(3.3v) short-circuit protection waveform vout2 2v/div. pg 2v/div. shdnb1 shdnb2 5v/div. 1ms/div. 1ms/div. start-up shutdown shdnb1 shdnb2 5v/div. vout2 2v / div. pg 2v / div. vin 2v/div. current limiting. (typ. 4.5a) iout1 2a/div. vout1 2v/div. 3.3v 4ms/div. 5v a fter 10ms(typ.), all the outputs are latched to off by scp. ch1 output short-circuits.
raa23021x r18ds0013ej0102 rev.1.02 page 14 of 34 jul 23. 2014 ch2(ldo) peak output current vs. output voltage (vin=5.0v) ch2(ldo) output voltage vs . output current (vin=5.0v) standby current vs. operating ambient temperature vout2=3.3v vout2=1.2v
raa23021x r18ds0013ej0102 rev.1.02 page 15 of 34 jul 23. 2014 ic surface temperature vs. time ch1 and ch2 operation (normal mode) vin=5v ch1:3.3v, 2a ch2 : 1.8v, 0.3a t a = 25 measured on renesas evaluation board temperature derating curve
raa23021x r18ds0013ej0102 rev.1.02 page 16 of 34 jul 23. 2014 pakage tempereture rise vs. iout vin=5.0v maximum iout vs. ambient tempereture vin=5.0v note : when calculate the package temperature with both ch1 and ch2 operation, reference these data. onl y ch1 o p eration onl y ch2 o p eration onl y ch1 o p eration onl y ch2 o p eration
raa23021x r18ds0013ej0102 rev.1.02 page 17 of 34 jul 23. 2014 control block shdnb1, shdnb2: on/off setting shdnb1 shdnb2 ch1 ch2 l l off off h l start-up in order of ch1 and ch2 stop ch1 and ch2 at the same time l h start-up in order of ch2 and ch1 stop ch1 and ch2 at the same time h h start-up ch1 and ch2 at the same time stop ch1 and ch2 at the same time note: l: low level, h: high level off: circuit stand-by, on: circuit operation status when both shdnb1 and shdnb2 are h, r aa23021x continues operation even if one of them is turned to l. raa23021x stops when both of them are turned l. dstb: ic ultra low-power mode setting dstb ic operation l normal operation h ultra low-power mode operati on (ch1: stop, ch2: operation) note: l: low level, h: high level
raa23021x r18ds0013ej0102 rev.1.02 page 18 of 34 jul 23. 2014 output status v reg pin status shdnb1 shdnb2 dstb v reg l l l or h agnd h l l 2.4 v l h h h h l h agnd l h h h note: l: low level, h: high level ch1, ch2 output pin status ch1 ? ch2 status ch1 ch2 lout1 out2 stop pgnd (discharge circuit: on)* agnd (discharge circuit: on) operation pulse (vp in1 or pgnd) set voltage note: ch1 discharge circuit is ?on? during ultra low-power mode. pg pin status (ch1, ch2 output detect) ic operation status pg output status shdnb pin dstb pin ch1, ch2 output status shdnb1 = l shdnb2 = l l or h stop hiz shdnb1 = h or shdnb2 = h l ch1 or ch2 output voltage is under 90% of the set voltage l ch1 and ch2 output voltage are ov er 90% of the set voltage hiz h ch1: stop ch2: operation (both output voltage is over 90% of setting voltage and under 90%) hiz note: l: low level, h: high level, hiz: high impedance caution: when both ch1 and ch2 output voltage start up over 90%, there is delay time (under 2ms) before pg pin becomes hiz. when using power good (pg pin), connect it to ch1 or c h2 output. recommended value of pull-up resistor is 100k ? .
raa23021x r18ds0013ej0102 rev.1.02 page 19 of 34 jul 23. 2014 timing chart vreg a vdd ch1 out shdnb1 ch2 out shdnb2 z input pg (open) 2.4 v 90 90 90 a nd pg ( connect to ch1 out or ch2 out ) ch1out or ch2out 2ms z output hiz hiz hiz hiz 2ms 2ms
raa23021x r18ds0013ej0102 rev.1.02 page 20 of 34 jul 23. 2014 operation of each block (overview) rise up sequencer the ic ?rise up? sequence feature has 3 patterns described below. the internal ?rise up? sequence capability does not need any additional external circuitry or components. pattern 1 : ch1 -> ch2 shdnb1 vout1 vout2 2ms 2ms pattern 2 : ch2 -> ch1 shdnb2 vout1 vout2 2ms 2ms pattern 3 : ch1 and ch2 at the same time shdnb1 shdnb2 vout1 vout2 2ms note1 : actuary, soft start begin after vreg rises up note2 : in all patterns, ch1 and ch2 shutdown starts at the same time.
raa23021x r18ds0013ej0102 rev.1.02 page 21 of 34 jul 23. 2014 soft start to limit the startup inrush current and output voltage overshoot , a soft start circuit is used to ramp up the reference voltage from 0 v to its final value linearly. the soft start time are fixed for both ch1 and ch2 are 2ms(typ.) and no additional components are needed. soft start feature grad ually increases the error amplifier (e/a) input threshold voltage by using the voltage that is generated by the digital soft start (dss) circuit in 64 steps. v out ii1, ii2 e/a1, e/a2 - + dss circuit 0.8v 64 steps shdnb1 shdnb2 vout1 vout2 vreg dss 0.8v lout1 64 steps 2ms note1 : this figure is the case of raa230215 note2 : this chart is the case that ch1 and ch2 start at the same time note3 : dss waveform cannot be observed from ic outside.
raa23021x r18ds0013ej0102 rev.1.02 page 22 of 34 jul 23. 2014 discharge circuit this ic has the discharge circuit for both ch1 and ch2. this enables a rapid discharge without an external mosfet. when shdnb pin is changed from high level to low, discharge switches of ch1 and ch2 turn on at the same time, and they discharge all capacitors whic h are connected to each output through lout1 and out2 pin. when avdd pin voltage becomes low level, discharge switches become off because there are no voltage to keep them on. the control voltage of discharge switches is vreg, and the discharge time of vreg capacitor is over 100ms when avdd voltage fall down, so even if shdnb pin is connected to avdd pin, the output voltage of ch1 and ch2 can be discharged because vreg voltage level can keep the discharge switches on. about calculation of discharge time, see page 30. power good power good (pg) is an open-drai n output that requires a pull ? up resistor (recommended value = 100k ? ). pg releases when the both ch1 and ch2 fb voltage and thus the output voltage rises above 90% of nominal regulation point. the pg goes low when the fb voltage falls below 90% of the regulation point. when both shdnb pins become low level, pg pin become high impedance (hiz) because vreg is used for pg control and it fall down at this time. so, if pg is connected to avdd, its status keep high level. pg pin must be connected to ch1 or ch2 output. this function can be used for sequence signal for other devices. note : these dashed arrow are discharge line. pgnd11, 12 lout11, 12 vpin11,12 out2 vpin2 discharge control ldo ch1 output control vin discharge control device b device a device c device d device e vreg
raa23021x r18ds0013ej0102 rev.1.02 page 23 of 34 jul 23. 2014 protection circuit view protection circuit function operation status reset common circuit (v reg , osc, etc.) output short-circuit protection (scp) * only ch1 detect ch1 output voltage dropping because of short-circuit, etc. (timer latch type) operation all the output are latched to off change shdnb1 pin and shdnb2 pin from high to low or drop av dd pin input voltage under the operation stop voltage (2.8 v) thermal shutdown circuit (tsd) detect increase of ic internal temperature (over 150c) (timer latch type) operation all the output are latched to off over current protection (ocp) * only ch2 detect ch2 over current operation ch2 output is down (ch1 continues operation) release over current status (under the output short-circuit current: 100 ma) under voltage lockout circuit (uvlo) detect dropping of av dd (ic power supply) operation *1 all the outputs are stop up av dd pin input voltage over the operation start voltage (2.9 v) note: the common circuit stops if avdd is lower than vreg. when ultra low-power mode, these prot ection circuits do not operate.
raa23021x r18ds0013ej0102 rev.1.02 page 24 of 34 jul 23. 2014 short-circuit protection circuit (ch1) when the voltage of ch1 drops, the voltage of the ii1 pin also drops. if it falls below the input detection voltage of the short-circuit protection circuit (under 75% of output voltage), the timer circuit starts operating. and after 10 ms, all the outputs are latched to off. at this time, common circuits (suc h as the internal power supply block, and oscillator, etc.) continue operating. when the short-circuit protection circuit is operating, to rese t the latch circuit, either change the level of the shdnb1 pin and shdnb2 pin from high to low or drop the level of the power supply voltage (av dd ) to the level below the operation stop voltage of the under voltage lockout circuit (2.8 v). ? timing chart (when ch1 is short circuited) shdnb1 (1) (2) (3) ii1 (1) the input detection voltage (1) at starting ? a short-circuit will not be detected while the ch1 is under going a soft start (that is, short-circuit protection is not triggered). if a short circuit occurs while ch1 is starting, short-circuit protection will star t after the soft start time elapses following startup. ? if a short-circuit occurs in a channel that is operating while another channel is being soft-started, short-circuit protection will start immediately. (2) short-circuit protection operation ? if a short circuit is detected in ch1 (ch1 ii pin voltage is lower than the input detection voltage except soft-stare period), the timer circuit starts operating. and after 10 ms, all the outputs are latched to off. ? common circuits (such as the internal power supply block, and oscillator, etc.) continue operating. (3) cancelling short-circuit protection ? to reset the latch circuit, either change the level of the shdnb1 pin and shdnb2 pin from high to low, or drop the level of the power supply voltage (av dd ) to the operation stop voltage of the under voltage lockout circuit (2.8 v).
raa23021x r18ds0013ej0102 rev.1.02 page 25 of 34 jul 23. 2014 thermal shutdown circuit (timer latch type) after overheating has been detected (shutdown temperature: 150c or higher), the timer circuit starts operating (as same as scp). and after 10 ms, all the outputs are latched to off. common circuits (such as the internal power supply block, and oscillator, etc.) continue operating. when the thermal shutdown circuit is operating, either change the level of the shdnb1 pin and shdnb2 pin from high to low, or drop the level of the power supply voltage (av dd ) to the operation stop voltage of the under voltage lockout circuit (2.8 v). when ultra low-power mode, this circuits does not operate. under voltage lockout circuit (auto recovery type) (1) under voltage lockout operation when the power supply voltage (av dd ) falls to the operation stop voltage (2.8 v), output from all channels stops. common circuits (such as the internal power supply block, and oscillator, etc.) continue operating. (2) restoring output once av dd voltage is restored to the operation start voltage (2 .9 v), the under voltage lockout operation is canceled and output automatically resumes. the output voltage cannot be restored while the under voltage lockout circuit is operating, not even by manipulating the shdnb pin. when ultra low-power mode, this circuits does not operate. current limiting ch1 operates under the current control m ode. if an overcurrent occurs, the curren t is limited on a pulse-by-pulse basis. if the current sensor detects an overcurrent, the current is limited and the switching operation of the power mosfet in the output stage stops until the next cycle. when the ch1 current is limited, the output voltage drops. if the ch1 ii pin voltage falls below the input detection voltage, the short-circuit protection circuit starts operating. reference data (unless otherwise specified, t a = 25c, av dd = vp in1 = 5.0 v) item symbol min typ max unit measurement condition current limit value ch1 current limet 1 i lim1_1 ? 4.5 ? a ch1out 3.3v ch1 current limet 2 i lim1_2 ? 4.5 ? a ch1out 1.2v note: these data are for reference a nd not guaranteed as specifications. reverse current protection (ch1) ch1 have a reverse current protection circuit. when the bottom of inductor current is under ground, low-side n-ch mosfet of output block is stopped, and ch1 operate as diode rectification. so, consumption current at light load can be reduced. over current protection (ch2) ch2 have a fold back type current protection circuit. if ov er current occur, pr otection operation is started and load current is limited (output short-circuit current: 100 ma). peak output current depend on output voltage. when vpin2=5v and vout2=3.3v,.it is over 550ma. when ultra low-power mode, this circuits does not operate.
raa23021x r18ds0013ej0102 rev.1.02 page 26 of 34 jul 23. 2014 ultra low-power mode this ic has the ultra-low power mode. by setting dstb pin in to high level, the ic operates in the ultra-low power mode, and ch2 (ldo) operates. then the consumption current is 25 a (typ.) and ch1 stops. if dstb pin is set from high level to low level, the ic operation changes to normal mode, and ch1 starts up with soft start. when ultra low-power mode, protec tion circuits does not operate. ? timing chart ch1 out ch1 out ch2 out ch2 out the output is continued. pg (open) pg (connect to ch1 out) pg (connect to ch2 out) hiz dstb ? input ? output v reg
raa23021x r18ds0013ej0102 rev.1.02 page 27 of 34 jul 23. 2014 advance on designing setting output voltage (when the output voltage is set by external resistor) the output voltage settings are shown in the figures below. the output voltag e can be calculated by the equations shown in these figures. 0.8v(typ.) v out (output voltage) r1 r2 e/a1, e/a2 v out = (1+r1/r2) 0.8 ? + [setting output voltage of ch1, ch2 by external resistor] examples of r1 and r2 selection vout 0.9v 1.0v 1.05v 1.1v 1.18v 1.2v 1. 5v 1.8v 2.5v 3.3v r1 12k 16k 16k 15k 39k 15k 24k 30k 100k 75k r2 91k 62k 51k 39k 82k 30k 27k 24k 47k 24k output voltage accuracy (when the output voltage is set by external resistor) output voltage accuracy can be calculated by an equation below. v outacc is the output voltage accuracy (%). v ithacc is the e/a input threshold voltage accuracy (%). v out is the output voltage (v). r acc is the external resistor accuracy (%). so, each ch1 and ch2 output voltage accuracy is below. note : these equation don?t include vout fluctuation by load step transient.
raa23021x r18ds0013ej0102 rev.1.02 page 28 of 34 jul 23. 2014 handling of pins when not used connect unused pins as below. always connect avdd pin, vpin1 pin and vpin2 pin with power supplies, and connect pgnd1 pin and agnd with the ground. when dstb pin is not used:. pin number pin name connection 18 dstb agnd when shdnb1 pin is not used:. pin number pin name connection 20 shdnb1 agnd when shdnb2 pin is not used:. pin number pin name connection 19 shdnb2 agnd when pg pin is not used:. pin number pin name connection 12 pg agnd
raa23021x r18ds0013ej0102 rev.1.02 page 29 of 34 jul 23. 2014 inductor selection it is recommended to choose a inductor which ripple current ( ? il) becomes 20 to 40 % of iout(max). when ? il increases, inductor current peak raises, so ripple of vout gets larger and power loss increases. but, large inductor is required to lower ? il. ? il can be calculated by an equation below. fsw is 1mhz. peak current of inductor (ilpeak) can be calculated by an equation below. choose a inductor which saturation current is higher than ilpeak . inductor example note i temp : rated current by temperature rising i sat : rated current by inductance loss these inductors are examples. about inductor detail, contact each manufacturer ch output current inductor manufacturer inductance (uh) i temp (a) i sat (a) size (lxwxt, mm) ch1 less than 1.5a vlf504012mt-3r3m tdk 3.3 2.4 2.1 5x4x1.2 nrs4018t3r3mdgj taiyo yuden 3.3 2 2.3 4x4x1.8 744042003 wurth 3.3 1.9 1.8 4.8x4.8x1.8 1.5a to 3a ltf5022t-2r2n3r2-lc tdk 2.2 3.4 3.2 5.2x5x2.2 nr5024t2r2nmgj taiyo yuden 2.2 3.1 4.1 4.9x4.9x2.4 744062002 wurth 2.2 3.4 2.7 6.8x6.8x2.3 ltf5022t-1r5n3r6-lc tdk 1.5 3.4 3.2 5.2x5x2.2 nr6020t1r5n taiyo yuden 1.5 3.2 4 6x6x2 7440620015 wurth 1.5 4.3 4 6.8x6.8x2.3
raa23021x r18ds0013ej0102 rev.1.02 page 30 of 34 jul 23. 2014 output capacitor selection each channel of raa23021x has a phase compensation circuit which is optimized to each operation. in order to operate stably with the phase compensation, connect the output capacitor : dc/dc converter (ch1) : over 22uf ldo (ch2) : over 10uf ceramic capacitor can be used for output capacitor. it has low esr, so vout ripple is decreased. vout ripple ( ? vrpl) can be calculated by an equation below. input capacitor selection recommended input capacitor of dc/dc co nverter can be calculated by an equa tion below. connect the capacitor that value is over calculated one. about ldo, connect the capacito r that value is over 10uf.
raa23021x r18ds0013ej0102 rev.1.02 page 31 of 34 jul 23. 2014 feedback capacitor when raa230215 (output voltage is set by external resistors) is used, connect 100pf capacitor in parallel to high side output voltage setting resistor of ch1 to improve phase characteristic. don?t use at ch2. discharge time raa23021x has discharge circuit. discharge time can be calculated by an equation below. v dc is a voltage after tdc(s). c all is sum of all capacitance which are connected to the output of raa23021x (output capacitor, bypass capacitor around mcu, etc.). r ondc is on resistance of discharge circuit. v out r1 r2 ii1 r a a230215 100pf
raa23021x r18ds0013ej0102 rev.1.02 page 32 of 34 jul 23. 2014 notes on use connection of power input pin be sure to apply the same voltage to av dd pin and vp in11 pin. vp in2 input voltage must be same or less than av dd . pg connection when using power good (pg pin), connect it to ch1 or ch2 output. if pg is connected to av dd , pg outputs high (av dd ) when shdnb1 and shdnb2 is low (because pg is high impedance when shdnb1 and sdhnb2 is low). protection circuit at ultra low-power mode when ultra low-power mode, all prot ection circuits do not operate. actual pattern wiring to actually perform pattern wiring, separate the ground of the control signals (agnd) from the ground of the power signals (pgnd), so that these signals do not have common im pedance as much as possible. in addition, lower the high- frequency impedance by using a capacitor, so that noise is not superimposed on the v reg pin. connection of exposed pad raa23021x has an exposed pad on the bottom to improve radiation performance. on the mounting board, connect to agnd. connection of component ground when connecting a component to ground, connect to the ground below. component connect ground ch1 input capacitor, ch1 output capacitor pgnd ch2 input capacitor, ch2 output capacitor ch1 output voltage setting resistor (low side) ch2 output voltage setting resistor (low side) vreg capacitor agnd fixed usage of control input pin when using fixed input pins shdnb1, shdnb2, dstb input pins, connect each input to the pins listed below. input pin connect pin fixed to low level fixed to high level shdnb1 agnd av dd shdnb2 agnd av dd dstb agnd av dd connection of test pin connect each test pin to the pins listed below. test pin connect pin test1 agnd test2 vreg test3 open
raa23021x r18ds0013ej0102 rev.1.02 page 33 of 34 jul 23. 2014 the case short-circuit is not protected. if a power supply of raa23021x has current limit which is under ch1 current limit 4.5a (typ.), the voltage and thus avdd falls when ch1 output short-circuits. if it becomes under operation stop voltage of uvlo (typ. 2.8v), all the output voltage are stopped. then ch1 short-circuit is stopped, so avdd recovers. after it becomes above operation start voltage of uvlo (typ. 2.9v), ch1 and ch2 output are restored, and ch1 short-circuits again. a large current may flow continuously by repeating these operations. to avoid devices destruction by the large current, set the power supply current limit higher or use a fuse into the power supply line. vin 2v/div. large current flows continuously. iout1 2a/div. vout1 2v/div. 3.3v 4ms/div. 5v ch1 output short-circuits. in this case, vin current limit = 1.5a
raa23021x r18ds0013ej0102 rev.1.02 page 34 of 34 jul 23. 2014 package dimensions 20-pin htssop
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history raa23021x datasheet rev. date description page summary 1.01 jan 17, 2014 - first ed ition of datasheet issued 1.02 jul 23, 2014 2 circuit example, added 7 range of ?circuit operation current 2? and ?internal power supply voltage?, changed
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao rd., putuo district, shanghai, china tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2014 renesas electronics corporation. all rights reserved. colophon 3.0

▲Up To Search▲

Price & Availability of RAA230215GSB

	To Download RAA230215GSB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .